Generally, a combinational logic circuit operating at high speed has an additional circuit for testing the combinational logic. The additional circuit is called a scan circuit. The scan circuit can be set to a state for testing and observing the state of the combinational logic using flip-flop circuits connected to an input terminal and an output terminal of the combinational logic.
A logic circuit for carrying out the delay test of a combinational logic is disclosed, for example, in "A logic chip delay-test method based on system timing" IBM Journal of Research and Development, Vol. 34, No. 2/3 pp. 299-313 (Mar./May 1990).
Hereunder, we will explain the above-mentioned prior art referring to FIGS. 18 to 21.
Referring to FIG. 18, 10A, 10B, 10C and 10D denote flip-flop circuits. The flip-flop circuits 10A and 10B correspond to a flip-flop circuit 10 shown in FIG. 1 mentioned later. The flip-flop circuits 10C and 10D correspond to a flip-flop circuit 13 shown in FIG. 1. The flip-flop circuits 20A, 20B, 20C and 20D are the same as flip-flop circuit 20 shown in FIG. 19. The operations of the flip-flop circuits 10A, 10B, 10C and 10D and the flip-flop circuits 20A, 20B, 20C and 20D are shown by FIG. 4 and FIG. 20, respectively. Numerals 2013 and 2014 show system clocks which are not overlapped and are used for operating an actual system. Numerals 2011 and 2012 show scan clocks. The scan clocks 2011 and 2012 are used together with a scan-in data pin 2015 and a scanout data pin 2016 for carrying out initialization and observation of these flip-flop circuits independently from a system logic. Hereunder, we will explain a procedure for carrying out a delay test of a path 2000 shown in FIG. 18 referring to the time chart shown in FIG. 21. For initializing all the flip-flop circuits and a combinational logic 200, the system clocks 2013 and 2014 are turned OFF, namely made to zero levels, at first, then the scan clocks 2011 and 2012 are alternately turned to ON states giving data to the scan-in data pin 2015 as shown in 2101 of FIG. 21 so that the data to be initialized is shifted to the flip-flop circuit in order. Next the data of the flip-flop circuits 10A, 10B, 10C and 10D are stored in the flip-flop circuits 20A, 20B, 20C and 20D by turning the scan clock to OFF state and the system clock to ON state. Thereby, a change signal 2102 is transmitted to the path 2000 for changing from level 0 to level 1 or from level 1 to level 0 of the flip-flop circuits 20A, 20B, 20C and 20D. After a transmission delay time of the path 2000 has passed, the system clock 2014 is turned to ON state as shown in 2103 of FIG. 21 so that the flip-flop circuit 10C stores the output signal of the path 2000. Then, the flip-flop circuit 10C stores different signals corresponding to normal state and abnormal state of the delay transmission time of the channel 2000. Lastly, the scan clocks 2011 and 2012 are alternately turned to ON states as shown in 2104 of FIG. 21, and the states of the flip-flop circuit 10C are shifted to the scan-out pin 2016 for observing the stored signal of the flip-flop circuit 10C.
Since the prior art mentioned above has a double latch structure of the flip-flop circuits in the input and output sides of the combinational logic which is to carry out the delay test, the transmission delay time of the path between the flip-flop circuits is longer than a single flip-flop circuit so that the performance of the circuit is lowered. Further, since the prior art can use either one of the system clock or the scan clock as a clock for the second flip-flop circuits 20A, 20B, 20C and 20D provided at both sides of the combinational logic, the additional element 21 is necessary on the clock channel compared with the circuit in which only the system clock is used. When the element is added on the clock channel, fluctuation of the clock skew is increased and power consumption is increased thereby increasing the drive performance of the clock pulse.